1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a method of fabricating metal lines and trenches separating metal lines.
2. Description of the Related Art
The implementation of integrated circuits involves connecting isolated circuit devices through specific electrical pathways. Where integrated circuits are implemented in silicon, it is necessary, therefore, to initially isolate the various circuit devices built into the silicon substrate from one another. The circuit devices are thereafter interconnected to create specific circuit configurations through the use of global interconnect or metallization layers and local interconnect layers.
A global interconnect or metallization layer consists of a plurality of conductor lines or traces separated by grooves or trenches that are filled with an insulating material such as silicon dioxide, various types of glasses or one of many polymeric materials commonly used for interlevel dielectric layers. Various types of conductor materials have been historically used for global interconnect layers, the most common of these being aluminum, either in relatively pure form or mixed with small percentages of another conducting material, such as copper. Aluminum has been widely employed as a global interconnect material, due to its relatively good adherence to silicon and silicon dioxide structures, acceptable sheet resistance and low cost.
In most conventional methods for fabricating an aluminum global interconnect layer, a semiconductor wafer is blanket coated with a layer of aluminum by chemical vapor deposition ("CVD") or physical vapor deposition ("PVD"). The aluminum layer is then masked with a photoresist that is patterned, that is, exposed and developed, to cover the portions of the aluminum layer that will remain and constitute the individual conductor lines following a subsequent etch of the exposed portions of the aluminum. Where the critical dimension for the process used to pattern the aluminum will be less than about one micron, an anti-reflective coating layer is frequently applied to the upper surface of the aluminum layer prior to application and patterning of the resist. Following patterning of the photoresist, the exposed portions of the aluminum layer are etched down to the underlying subsurface, which is ordinarily the upper surface of an interlevel dielectric layer but may also be an underlying conductor layer and/or diffusion barrier. Dry anisotropic etching is frequently used to etch the aluminum layer. In most cases, the combination of the chemistry used to anisotropically etch the aluminum and the liberation of resist particles during the etch yields trenches between adjacent metal lines with nearly vertical sidewalls.
There are several disadvantages associated with conventional methods of patterning aluminum global interconnect layers. Many of these disadvantages can be traced to difficulties introduced into semiconductor fabrication as the result of increased packing density in design rules. The patterning of global aluminum interconnect layers in sub-0.3 .mu.m technology frequently requires the etching of aluminum at very high aspect ratios, sometimes greater than 3:1 or 4:1. Such high aspect ratios combined with the relatively small lateral dimensions of trenches between adjacent metal lines can lead to significant problems during subsequent interlevel dielectric layer deposition processes. The difficulty stems from the fact that subsequently applied interlevel dielectric layers may not sufficiently adhere to the bottom corners of such high aspect ratio trenches and thus result in voids in, and/or cracking of, the interlevel dielectric material at the corners, which can lead to a variety of conductivity problems. The nearly vertical sidewalls established by most conventional aluminum etching processes does not favor dielectric adhesion and thus exacerbates the potential for void and/or cracked formation.
Another disadvantage associated with conventional aluminum processing is the limitation on critical dimension imposed by the photolithographic limit of the prevailing photolithographic patterning technology. The fabrication of increasingly smaller features in integrated circuits is dependent on the availability of increasingly higher resolution optical lithography equipment. Designers of optical lithography equipment have employed several techniques to combat the deleterious effects of light diffraction. Some of these techniques include decreasing the wave length of the illuminating light, increasing the numerical aperture of the system, increasing the contrast of the resist by modifying resist chemistry or by creating entirely new resists, and adjusting the coherence of the optical system. Even with the availability of these various techniques for increasing the resolution of optical lithography equipment, the best of conventional optical lithography systems have a resolution limit of about 0.2 .mu.m when used in conjunction with resists in the 1.0 .mu.m or greater range are used, and may still produce images with bridged patterns due to depth of focus limitations. Accordingly, the effective critical dimension between metal lines using conventional etching techniques and lithographic patterning processes is about 0.3 .mu.m. Packing density for metallization is thus limited to these geometries in the absence of techniques for working around the limitations in optics.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.